The FASTER tool-chain input will be based on hardware description languages or high-level programming languages with an initial decomposition described using existing formalisms (such as OpenMP). This input will be transformed to the corresponding task graph, which in turn will be partitioned in space and time using new algorithms derived from graph theory. We will pursue a task-cluster definition of a system specification by detecting recurrent structures in the specification, and consider them as candidates for reconfiguration. FASTER will support both region- and micro-reconfiguration (a technique that reconfigures very small parts of the device), an ability that opens up a new range of application opportunities for run-time reconfiguration.

FASTER will develop novel techniques for optimizing and verifying static and dynamic aspects of a reconfigurable design, while minimizing run-time overheads on speed, area and power consumption. FASTER will also provide a powerful run-time system that will be able to run on multiple reconfigurable platforms and manage the various aspects of parallelism and adaptivity with reduced overhead.

To demonstrate the effectiveness of the FASTER tool-chain, we will use three complex applications from different application domains: (a) Reverse Time Migration (RTM), a computational seismography algorithm, (b) Global Illumination and Image Analysis, and (c) a Network Intrusion Detection System (NIDS). We will evaluate the effect of the FASTER tool flow on designer productivity in the design and verification process. We will also use prototype platforms to evaluate the speed, cost, and power consumption of the applications implemented within FASTER.
Project performance targets:

• 20% productivity improvement due to seamless implementation and verification of dynamically changing systems
• 50% total ownership cost reduction for NIDS and RTM systems
• 2x performance improvement under power constraints for Global Illumination and Image Analysis