Contract number
287804

Ccoordinator
FORTH-ICS

Contact person
Dionisios Pnevmatikatos

Community contribution
2.8 M€

Start date
September 1st, 2011

Duration
36 months

FASTER project on CORDIS

EUROPEAN COMMISSION
Seventh Framework Programme
Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Publications

    2015

  1. Davide Pagano, Mikel Vuka, Marco Rabozzi, Riccardo Cattaneo, Donatella Sciuto, Marco D. Santambrogio: Thermal-Aware Floorplanning for Partially-Reconfigurable FPGA-based Systems, Design, Automation and Test in Europe, 2015. DATE ’15, accepted to appear, Grenoble, France, 9-13 March 2015
  2. Eddie Hung, Joshua Levine, Edward Stott, George Constantinides and Wayne Luk. "Delay-Bounded Routing for Shadow Registers", FPGA 2015 (to appear)
  3. James Arram, Wayne Luk and Peiyong Jiang. "Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment", FPGA 2015 (to appear)
  4. Xinyu Niu, Wayne Luk and Yu Wang. "EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access". FPGA 2015 (to appear)
  5. G. Charitopoulos, I. Koidis, K. Papadimitriou, D. Pnevmatikatos, "Realistic Hardware Task Scheduling for Partially Reconfigurable FPGAs", HiPEAC Workshop on Reconfigurable Computing (WRC), Amsterdam, Netherlands, Jan 2015 (submitted)

  6. 2014

  7. Poona Bahrebar and Dirk Stroobandt. “Adaptive and Reconfigurable Fault-tolerant Routing Method for 2D Networks-on-Chip,” ReConfig 2014 - Cancun, Mexico, December 8-10, 2014
  8. Tom Davidson and Dirk Stroobandt. “Data path analysis for Dynamic Circuit Specialisation,” ReConfig 2014 - Cancun, Mexico, December 8-10, 2014
  9. Amit Kulkarni, Tom Davidson, Karel Heyse and Dirk Stroobandt. “Improving Reconfiguration Speed for Dynamic Circuit Specialization using Placement Constraints,” ReConfig 2014 - Cancun, Mexico, December 8-10, 2014
  10. Brahim Al Farisi, Karel Heyse, Karel Bruneel, João Cardoso, and Dirk Stroobandt. “Enabling FPGA routing configuration sharing in dynamic partial reconfiguration.” In Design Automation for Embedded Systems (2014): 1-33
  11. Brahim, Al Farisi, Karel Heyse and Dirk Stroobandt. “Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits.” In The international Conference on Field-Programmable Technology (ICFPT), (2014) (accepted, not yet published)
  12. Elias Vansteenkiste, Brahim Al Farisi, Karel Bruneel and Dirk Stroobandt. “TPaR : place and route tools for the dynamic reconfiguration of the FPGA's interconnect network.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 33(3), pp. 370-383 (2014)
  13. Fabrizio Spada, Alberto Scolari, Gianluca C. Durelli, Riccardo Cattaneo, Marco D. Santambrogio, Donatella Sciuto, Dionisios N. Pnevmatikatos, Georgi Gaydadjiev, Oliver Pell, Andreas Brokalakis, Wayne Luk, Dirk Stroobandt, Danilo Pau: FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board. ISPA 2014: 134-141
  14. Riccardo Cattaneo, Riccardo Bellini, Gianluca Durelli, Christian Pilato, Marco D. Santambrogio, and Donatella Sciuto. 2014. PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures. In Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops (IPDPSW '14). IEEE Computer Society, PHOENIX (Arizona) USA, 243-250
  15. A.A.M. Bsoul, S.J.E. Wilton, K.H. Tsoi and W. Luk. "An FPGA Architecture and CAD Flow Supporting Dynamically-Controlled Power Gating", IEEE Trans. on Very Large Scale Integration (VLSI) Systems. (accepted for publication)
  16. Q. Liu, T. Mak, T. Zhang, X. Niu, W. Luk and A. Yakovlev, "Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems," IEEE Trans. on Very Large Scale Integration (VLSI) Systems on (Volume:PP , Issue: 99 )
  17. D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Bohm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M. D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste. "FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration", Elsevier Journal on Microprocessors and Microsystems (MICPRO), (2014)[.pdf] / [link]
  18. Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker and Wayne Luk. "Low Latency FPGA Acceleration of Market Data Feed Arbitration", ASAP, 2014
  19. G. Charitopoulos, K. Papadimitriou, D. Pnevmatikatos, “Run-time Hardware Task Scheduling for Partially Reconfigurable FPGAs” (poster), 10th Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Fiuggi, Italy, July 2014
  20. Durelli, Gianluca; Spada, Fabrizio; Cattaneo, Riccardo; Pilato, Christian; Pau, Danilo; Santambrogio, Marco D., "Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration," Parallel & Distributed Processing Symposium Workshops (IPDPSW), 2014 IEEE International , vol., no., pp.236,242, 19-23 May 2014[.pdf]
  21. Rabozzi, Marco; Lillis, John; Santambrogio, Marco D., "Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming," Field-Programmable Custom Computing Machines (FCCM), 2014 IEEE 22nd Annual International Symposium on , vol., no., pp.186,193, 11-13 May 2014[.pdf]
  22. Amit Kulkarni, Karel Heyse, Tom Davidson, and Dirk Stroobandt. “Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs.” In FPGA World 2014, Stockholm (http://www.fpgaworld.com/)[.pdf]
  23. Heyse, Karel, Dirk Stroobandt, Oliver Kadlcek, and Oliver Pell. "On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure." In Reconfigurable Computing: Architectures, Tools, and Applications, pp. 85-96. Springer International Publishing, 2014.[.pdf]
  24. Eddie Hung, Tim Todman, and Wayne Luk "Transparent insertion of latency-oblivious logic onto FPGAs" FPL 2014[.pdf]
  25. Maciej Kurek, Tobias Becker, Thomas C.P. Chau and Wayne Luk. "Automating Optimization of Reconfigurable Designs," International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014[.pdf]
  26. Thomas C.P. Chau et.al. "SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications." International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014[.pdf]
  27. C. Vatsolakis, K. Papadimitriou, D. Pnevmatikatos, "Enabling Dynamically Reconfigurable Technologies in Mid Range Computers Through PCI Express", HiPEAC Workshop on Reconfigurable Computing (WRC), Vienna, Austria, Jan 2014 [.pdf]
  28. D. Pnevmatikatos, T. Becker, A. Brokalakis, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, D. Pau, M. D. Santambrogio, D. Sciuto, D. Stroobandt, "Effective Reconfigurable Design: the FASTER Approach", n Proc. 10th International Symposium on Applied Reconfigurable Computing (ARC), Vilamoura, Algarve, Portugal, Apr 14-16, 2014 [.pdf]

  29. 2013

  30. Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, and Dirk Stroobandt. “Efficient Implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.” In Proceedings of the 23rd International Conference on Field Programmable Logic and Applications, 1–8, 2013
  31. James Arram, Wayne Luk and Peiyong Jiang. "Reconfigurable filtered acceleration of short read alignment", FPT 2013
  32. Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt. “A connection-based router for FPGAs.” In International Conference on Field-Programmable Technology, Proceedings, pp. 326-329 (2013)[.pdf]
  33. Tim Todman and Wayne Luk, “Runtime assertions and exceptions for streaming systems”, FPL 2013[.pdf]
  34. Xinyu Niu, Jose G. F. Coutinho, Wang Yu and Wayne Luk. "Dynamic Stencil: Effective Exploitation of Run-time Resources in Reconfigurable Clusters". FPT, pp. 214-221, 2013[.pdf]
  35. Thomas C.P. Chau, Ka-Wai Kwok, Gary C.T. Chow, Kuen Hung Tsoi, Zion Tse, Peter Y.K. Cheung and Wayne Luk. "Acceleration of Real-time Proximity Query for Dynamic Active Constraints" FPT, pp. 206-213, 2013.[.pdf]
  36. Paul Grigoras, Xinyu Niu, Jose G. F. Coutinho, Wayne Luk, Jacob Bower and Oliver Pell. "Aspect Driven Compilation for Dataflow Designs" ASAP 2013[.pdf]
  37. Xinyu Niu, Jose G. F. Coutinho and Wayne Luk. "A Scalable Design Approach for Stencil Computation on Reconfigurable Clusters". FPL 2013[.pdf]
  38. K. Heyse, K. Bruneel and D. Stroobandt, "Proving Correctness of Regular Expression Matchers with Constrained Repetition", ELECTRONICS LETTERS, vol. 49(1), pp. 41-42, Jan, 2013
  39. C. Pilato, R. Cattaneo, G. Durelli, A. Nacci, M.D. Santambrogio and D. Sciuto, "A2B: a Framework for the Fast Prototyping of Reconfigurable Systems", in Proc. 7th HiPEAC Workshop on Reconfigurable Computing (WRC), pp. 1-10, Berlin, Germany, Jan 21, 2013 [.pdf] / [slides]
  40. X. Niu, T. C. P. Chau, Q. Jin, W. Luk and Q. Liu, "Automating Resource Optimisation in Reconfigurable Design", in Proc. 21st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 275-275, Monterey, CA, US, Feb 11-13, 2013 [poster]
  41. C. Ciobanu, G. Gaydadjiev, "Separable 2D Convolution with Polymorphic Register Files", in Proc. 26th International Conference on Architecture of Computing Systems (ARCS), pp. 317-328, Prague, Czech Republic, Feb 19-22, 2013 [.pdf] / [slides]
  42. B. Al Farisi, K. Bruneel, J. M. P. Cardoso and D. Stroobandt, "An Automatic Tool Flow for the Combined Implementation of Multi-mode Circuits", in Proc. Design, Automation, and Test in Europe Conference and Exhibition (DATE), pp. 821-826, Grenoble, France, Mar 18-22, 2013 [.pdf] / [slides]
  43. M. Kurek, T. Becker and W. Luk, "Parametric Optimization of Reconfigurable Designs Using Machine Learning", 9th International Symposium on Applied Reconfigurable Computing (ARC), pp. 134-145, Los Angeles, CA, US, Mar 25-27, 2013 [.pdf]
  44. J. Arram, K. H. Tsoi, W. Luk and P. Jiang, "Reconfigurable Acceleration of Short Read Mapping", in Proc. 21st IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 210-217, Seattle, WA, US, Apr 28-30, 2013 [.pdf]
  45. G. Durelli, A. A. Nacci, R. Cattaneo, C. Pilato, D. Sciuto and M.D. Santambrogio, "A Flexible and Reconfigurable Interconnection Structure for FPGA Dataflow Applications", in Proc. 20th Reconfigurable Architectures Workshop (RAW), Boston, MA, US, May 20-21, 2013 [.pdf] / [slides]
  46. D. Sciuto, M.D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou and D. Stroobandt, "The FASTER Vision for Designing Dynamically Reconfigurable Systems", in Proc. International Conference on IC Design and Technology (ICICDT), Pavia, Italy, May 29-31, 2013 [.pdf] / [slides]
  47. C. B. Ciobanu, D. N. Pnevmatikatos, K. D. Papadimitriou, G. N. Gaydadjiev, "FASTER Run-time Reconfiguration Management", 27th International Conference on Supercomputing (ICS), pp. 463-464, Eugene, OR, US, June 10-14, 2013 [.pdf] / [poster]
  48. T. C. P. Chau, J. Targett, M. Wijeyasinghe, W. Luk, P. Y. K. Cheung, B. Cope, A. Eele and J. Maciejowski, "Accelerating Sequential Monte Carlo Method for Real-time Air Traffic Management", In Proc. International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Edinburgh, Scotland, June 13-14, 2013 [.pdf]
  49. F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto and A. Tumeo. "Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems", in Proc. 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 47-54, Torino, Italy, June 25-27, 2013 [.pdf] / [slides]
  50. R. Cattaneo, C. Pilato, M. Mastinu, O. Kadlcek, O. Pell and M.D. Santambrogio, “Runtime Adaptation on Dataflow HPC Platforms”, in Proc. 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), pp. 84-91, Torino, Italy, June 25-27, 2013 [.pdf] / [slides]
  51. C. Pilato, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio and D. Sciuto, "A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems", in Proc. 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), Torino, Italy, June 25-27, 2013 [.pdf] / [slides]
  52. F. Abouelella, T. Davidson, W. Meeus, K. Bruneel and D. Stroobandt, "How to Efficiently Implement Dynamic Circuit Specialization Systems?", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 18, issue 3, July, 2013
  53. R. Cattaneo, X. Niu, C. Pilato, T. Becker, W. Luk and M.D. Santambrogio, "A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing", in Proc. 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2013), Darmstadt, Germany, July 10-12, 2013 [.pdf] / [slides]
  54. C. Ciobanu, G. Gaydadjiev, C. Pilato and D. Sciuto, "Dataflow Computing with Polymorphic Registers", in Proc. IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS), Samos, Greece, July 15-18, 2013 [.pdf]
  55. B. Al Farisi, E. Vansteenkiste, K. Bruneel and D. Stroobandt, "A Novel Tool Flow for Increased Routing Configuration Similarity in Multi-mode Circuits", in Proc. IEEE Computer Society Annual Symposium on VLSI, Natal, Brazil, Aug 5-7, 2013 [.pdf] / [slides]
  56. B. Al Farisi, K. Bruneel and D. Stroobandt, "StaticRoute: A Novel Router for the Dynamic Partial Reconfiguration of FPGAs", in Proc. 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, Sep 2-4, 2013 [.pdf] / [slides]
  57. T. Todman and W. Luk, "Runtime Assertions and Exceptions for Streaming Systems", in Proc. 23rd IEEE International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, Sep 2-4, 2013 [.pdf]
  58. T. Todman, S. Stilkerich and W. Luk, "Using Statistical Assertions To Guide Self-Adaptive Systems", in Proc. 2nd Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), Porto, Portugal, Sep 5, 2013 [.pdf]
  59. X. Niu, T. C. P. Chau, Q. Jin, W. Luk and Q. Liu, "Automating Elimination of Idle Functions by Run-time Reconfiguration", in Proc. 21st IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Seattle, WA, US, Apr 28-30, 2013 [.pdf]
  60. T. C. P. Chau, X. Niu, A. Eele, W. Luk, P. Y. K. Cheung and J. Maciejowski, "Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications", in Proc. 9th International Symposium on Applied Reconfigurable Computing (ARC), Los Angeles, CA, US, Mar 25-27, 2013 [.pdf]
  61. R. Cattaneo, C. Pilato, G. Durelli, M. D. Santambrogio, D. Sciuto, "SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs", in Proc. IEEE International Symporium on Rapid System Prototyping (RSP), pp. 102-108, Montreal, QC, Oct 3-4, 2013 [.pdf] / [slides]
  62. Y. Wang, X. Zhou, L. Wang, J. Yan, W. Luk, C. Peng, and J. Tong, "SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model", IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2179-2192, December 2013 [.pdf]

  63. 2012

  64. E. Vansteenkiste, K. Bruneel and D. Stroobandt, "A Connection Router for the Dynamic Reconfiguration of FPGAs", in Proc. 8th International Symposium on Applied Reconfigurable Computing (ARC), Hong Kong, Mar 19-23, 2012 [.pdf]
  65. K. Heyse, Brahim Al Farisi, K. Bruneel and D. Stroobandt, "Automating Reconfiguration Chain Generation for SRL-based Run-time Reconfiguration", in Proc. 8th International Symposium on Applied Reconfigurable Computing (ARC), Hong Kong, March 19-23, 2012 [.pdf] / [slides]
  66. K. H. Tsoi, T. Becker and W. Luk, "Modelling Reconfigurable Systems in Event Driven Simulation", In Proc. 4th International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Okinawa, Japan, May 31-June 1, 2012 [.pdf]
  67. M. D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G. C. Durelli and D. Sciuto, “Smart Technologies for Effective Reconfiguration: The FASTER Approach”, In Proc. 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK, July 9-11, 2012 [.pdf] / [slides]
  68. K. Papadimitriou, C. Vatsolakis and D. Pnevmatikatos, "Acceleration of Computationally-Intensive Kernels in the Reconfigurable Era", In Proc. 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), York, UK, July 9-11, 2012 [.pdf]
  69. T. Davidson, Fatma Mostafa Mohamed Ahmed Abouelella, K. Bruneel and D. Stroobandt, “Dynamic Circuit Specialisation for Key-based Encryption Algorithms and DNA Alignment”, Hindawi International Journal Of Reconfigurable Computing (IJRC), Vol. 2012, pp. 1-13, 2012 [.pdf]
  70. T. Todman and W. Luk, “Verification of Streaming Designs by Combining Symbolic Simulation and Equivalence Checking”, in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  71. X. Niu, Q. Jin, W. Luk, Q. Liu and O. Pell, "Exploiting Run-Time Reconfiguration in Stencil Computation", in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  72. A. Bonetto, A. Cazzaniga, G. Durelli, C. Pilato, D. Sciuto and M. D. Santambrogio, "An Open-source Design and Validation Platform for Reconfigurable Systems", in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  73. C. Pilato, A. Cazzaniga, G. Durelli, A. Otero, D. Sciuto, and M. D. Santambrogio, "On The Automatic Integration of Hardware Accelerators into FPGA-based Embedded Systems", in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  74. F. Abouelella, K. Bruneel and D. Stroobandt, "Automatically Exploiting Regularity in Applications to Reduce Reconfiguration Memory Requirements", in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  75. K. Heyse, K. Bruneel and D. Stroobandt. "Mapping Logic to Reconfigurable FPGA Routing", in Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf] / [slides]
  76. E. Vansteenkiste, K. Bruneel and D. Stroobandt, "Maximizing the Reuse of Routing Resources in a Reconfiguration-Aware Connection Router", In Proc. 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug 29-31, 2012 [.pdf]
  77. T. Davidson, K. Bruneel and D. Stroobandt, "Identifying Opportunities for Dynamic Circuit Specialization", in Proc. Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), held in conjunction with the 22nd IEEE International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, Sep 1, 2012 [.pdf]
  78. D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M. D. Santambrogio, D. Sciuto, D. Stroobadt and T. Todman, “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”, in Proc. 15th Euromicro Conference on Digital System Design (DSD), Izmir, Turkey, Sep 5-8, 2012 [.pdf] / [slides]
  79. K. Papadimitriou, C. Pilato, D. Pnevmatikatos, M. D. Santambrogio, C. Ciobanu, T. Todman, T. Becker, T. Davidson, X. Niu, G. Gaydadjiev, W. Luk and D. Stroobandt, "Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration", 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Paphos, Cyprus, Dec 5-7, 2012 [.pdf] / [slides]
  80. T. Davidson, M. Merlier, K. Bruneel and D. Stroobandt, "A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA", Advances in Parallel Computing, vol. 22, pp. 611-618, 2012
  81. K. Heyse, K. Bruneel and D. Stroobandt, "Mapping Logic to Reconfigurable FPGA Routing", ICT.Open conference, Rotterdam, Oct 22-23, 2012
  82. Q. Liu, T. Todman, W. Luk and G. A. Constantinides, "Optimizing Hardware Design by Composing Utility-Directed Transformations", IEEE Transactions on Computers 61(12): 1800-1812, Dec, 2012 [.pdf]
  83. T. Todman, P. Boehm and W. Luk, "Verification of streaming hardware and software codesigns", in Proc. IEEE International Conference on Field-Programmable Technology (FPT), pp. 147-150, Seoul, Korea, Dec 10-12, 2012 [.pdf]

  84. 2011

  85. K. Bruneel, W. Heirman and D. Stroobandt, “Dynamic data folding with parameterizable FPGA configurations”, ACM Transactions On Design Automation Of Electronic Systems (TODAES), Vol. 16(4), pp. 43:1-43:29, Oct 2011 [.pdf]
  86. T. Becker, Q. Jin, W. Luk and S. Weston, "Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing", in Proc. IEEE International Conference on Reconfigurable Computing and FPGAs (ReConFig), Cancun, Mexico, Nov 30-Dec 2, 2011 [.pdf]